Propagation Delay of Static SR Flip-Flop in Microsoft Office Development Data Matrix in Microsoft Office Propagation Delay of Static SR Flip-Flop

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Example 7.2 Propagation Delay of Static SR Flip-Flop using microsoft office todeploy data matrix barcode in web,windows application barcode The transient data matrix barcodes for None response of the latch in Figure 7.8, as obtained from simulation, is plotted in Figure 7.10.

The devices are sized as described in Example 7.1, and a load of a single inverter. Page 305 Friday, January 18, 2002 9:09 AM Section 7.2 Static Latches and Registers is assumed fo Microsoft Office barcode data matrix r each latch output. The flip-flop is initially in the reset state, and an S-pulse is applied. As we can observe, this results first in a discharging of the Q output while Q stays at 0.

Once the switching threshold of the inverter M3-M4 is reached, the Q output starts to rise. The delay of this transient is solely determined by the M3-M4 inverter, which is hampered by the slow rise time at its input. From the simulation results, we can derive that tpQ and tpQ equal 120psec and 230psec, respectively.

. 2.0 Volts SET tpQ 1.0 Figure 7.

10 Transient response of SR flip-flop. 0.0 0.

9 1.0 1.1 1.

2 1.3 Time (nsec) 1.4 1.

5 Q tpQ Q. Problem 7.2 Complimentary CMOS SR FF Instead of us Microsoft Office Data Matrix 2d barcode ing the modified SR FF of Figure 7.8, it is also possible to use complementary logic to implement the clocked SR FF. Derive the transistor schematic (which consists of 12 transistors).

This circuit is more complex, but switches faster and consumes less switching power. Explain why..

Multiplexer-Based Latches There are man Microsoft Office barcode data matrix y approaches for constructing latches. One very common technique involves the use of transmission gate multiplexers. Multiplexer based latches can provide similar functionality to the SR latch, but has the important added advantage that the sizing of devices only affects performance and is not critical to the functionality.

Figure 7.11 shows an implementation of static positive and negative latches based on multiplexers. For a negative latch, when the clock signal is low, the input 0 of the multiplexer is selected, and the D input is passed to the output.

When the clock signal is high, the input 1 of the multiplexer, which connects to the output of the latch, is selected. The feedback holds the output stable while the clock signal is high. Similarly in the positive latch, the D input is selected when clock is high, and the output is held (using feedback) when clock is low.

A transistor level implementation of a positive latch based on multiplexers is shown in Figure 7.12. When CLK is high, the bottom transmission gate is on and the latch is. Page 306 Friday, January 18, 2002 9:09 AM DESIGNING SEQUENTIAL LOGIC CIRCUITS 7 . Negative Latch Positive Latch 1 D 0. Figure 7.11 Negative and positive latches based on multiplexers. CLK CLK transparent - ECC200 for None that is, the D input is copied to the Q output. During this phase, the feedback loop is open since the top transmission gate is off. Unlike the SR FF, the feedback does not have to be overridden to write the memory and hence sizing of transistors is not critical for realizing correct functionality.

The number of transistors that the clock touches is important since it has an activity factor of 1. This particular latch implementation is not particularly efficient from this metric as it presents a load of 4 transistors to the CLK signal..

CLK D Figure 7.12 Positive latch built using transmission gates. CLK It is possibl Microsoft Office data matrix barcodes e to reduce the clock load to two transistors by using implement multiplexers using NMOS only pass transistor as shown in Figure 7.13. The advantage of this approach is the reduced clock load of only two NMOS devices.

When CLK is high, the latch samples the D input, while a low clock-signal enables the feedback-loop, and puts the latch in the hold mode. While attractive for its simplicity, the use of NMOS only pass transistors results in the passing of a degraded high voltage of VDD-VTn to the input of the first inverter. This impacts both noise margin and the switching performance, especially in the case of low values of VDD and high values of VTn.

It also causes static power dissipation in first inverter, as already pointed out in 6. Since the maximum input-voltage to the inverter equals VDD-VTn, the PMOS device of the inverter is never turned off, resulting is a static current flow. 7.

2.4 Master-Slave Edge-Triggered Register. The most comm on approach for constructing an edge-triggered register is to use a masterslave configuration, as shown in Figure 7.14. The register consists of cascading a negative latch (master stage) with a positive latch (slave stage).

A multiplexer-based latch is used in this particular implementation, although any latch could be used. On the low phase of the clock, the master stage is transparent, and the D input is passed to the master stage output,.
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