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Copyright 1999 by John F. Wakerly Copying Prohibited in Software Generator 39 barcode in Software Copyright 1999 by John F. Wakerly Copying Prohibited




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Copyright 1999 by John F. Wakerly Copying Prohibited use software code 3/9 printer toattach uss code 39 with software Data Matrix Encoding Data DO NOT COPY DO NOT COPY DO Software barcode 39 NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. IN ODD I1 I2 I3 I4 ODD IM IN Figure 5-73 Cascading XOR gates: (a) daisy-chain connection; (b) tree structure. odd-parity circuit even-parity circuit 74x280. 5 . Combinational Logic Design Practices 74x280. SPEEDING UP THE XOR TREE DO NOT COPY DO NOT COPY DO Software 3 of 9 NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. 8 9 10 11 12 13 1 2 4. A B C (8) (9). A B C D E F G H I EVEN ODD (10). D E F (11) (12) (13). EVEN G H I (1) (2) (4). Figure 5-74 The 74x280 9-b Code 39 for None it odd/even parity generator: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol.. Figure 5-75 shows how a pa rity circuit might be used to detect errors in the memory of a microprocessor system. The memory stores 8-bit bytes, plus a parity bit for each byte. The microprocessor uses a bidirectional bus D[0:7] to transfer data to and from the memory.

Two control lines, RD and WR, are used to indicate whether a read or write operation is desired, and an ERROR signal is asserted to indicate parity errors during read operations. Complete details of the memory chips, such as addressing inputs, are not shown; memory chips are described in detail in \chapref{MEMORY}..

If each XOR gate in Figure Code-39 for None 5-74 were built using discrete NAND gates as in Figure 5-70(b), the 74x280 would be pretty slow, having a propagation delay equivalent to 4 3 + 1, or 13, NAND gates. Instead, a typical implementation of the 74x280 uses a 4-wide AND-OR-INVERT gate to perform the function of each shaded pair of XOR gates in the figure with about the same delay as a single NAND gate. The A I inputs are buffered through two levels of inverters so that each input presents just one unit load to the circuit driving it.

Thus, the total propagation delay through this implementation of the 74x280 is about the same as five inverting gates, not 13.. Copyright 1999 by John F. Wakerly Copying Prohibited Section 5.8 74x08. EXCLUSIVE OR Gates and Parity Circuits D[0:7] RD WR Figure 5-75 Parity generation and checking for an 8-bit-wide memory system. To store a byte into the m barcode code39 for None emory chips, we specify an address (not shown), place the byte on D[0 7], generate its parity bit on PIN, and assert WR. The AND gate on the I input of the 74x280 ensures that I is 0 except during read operations, so that during writes the 280 s output depends only on the parity of the D-bus data. The 280 s ODD output is connected to PIN , so that the total number of 1s stored is even.

To retrieve a byte, we specify an address (not shown) and assert RD; the byte value appears on DOUT[0 7] and its parity appears on POUT. A 74x541 drives the byte onto the D bus, and the 280 checks its parity. If the parity of the 9-bit word DOUT[0 7],POUT is odd during a read, the ERROR signal is asserted.

Parity circuits are also used with error-correcting codes such as the Hamming codes described in Section 2.15.3.

We showed the parity-check matrix for a 7-bit Hamming code in Figure 2-13 on page 59. We can correct errors in this code as shown in Figure 5-76. A 7-bit word, possibly containing an error, is presented on DU[1 7].

Three 74x280s compute the parity of the three bit-groups defined by the parity-check matrix. The outputs of the 280s form the syndrome, which is the number of the erroneous input bit, if any. A 74x138 is used to decode the syndrome.

If the syndrome is zero, the NOERROR_L signal is asserted (this signal also could be named ERROR). Otherwise, the erroneous. Copyright 1999 by John F. Wakerly Copying Prohibited DO NOT COPY DO NOT COPY DO barcode 39 for None NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. 4 5 6.
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