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Figure 5-10 Two more ways to GO, with mixed input levels: (a) with an AND gate; (b) with a NOR gate. in Software Development Code 39 Full ASCII in Software Figure 5-10 Two more ways to GO, with mixed input levels: (a) with an AND gate; (b) with a NOR gate. .NET EAN/UCC-13




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Figure 5-10 Two more ways to GO, with mixed input levels: (a) with an AND gate; (b) with a NOR gate. generate, create none none on none projectsterrek.com ean 13 generating vb.net READY_L REQUEST READY GO READY_L QR Code Module Size and Area DO NOT COP Y DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. GO GO_L (a none none ) (b) GO READY_L REQUEST_L GO_L (c) (d) REQUEST REQUEST_L (b) (a). bubble-to-bubble logic design Copyright 1999 by John F. Wakerly Copying Prohibited 5 . Combinational Logic Design Practices A SEL READY_L REQUEST_L DO NOT COP none for none Y DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. DATA B (b) A ASEL ADATA_L BDATA_L DATA BSEL = ASEL A + ASEL B B Figure 5-1 none for none 1 A 2-input multiplexer (you re not supposed to know what that is yet): (a) cryptic logic diagram; (b) proper logic diagram using active-level designators and alternate logic symbols.. To underst and the benefits of bubble-to-bubble logic design, consider the circuit in Figure 5-11(a). What does it do In Section 4.2 we showed several ways to analyze such a circuit, and we could certainly obtain a logic expression for the DATA output using these techniques.

However, when the circuit is redrawn in Figure 5-11(b), the output function can be read directly from the logic diagram, as follows. The DATA output is asserted when either ADATA_L or BDATA_L is asserted. If ASEL is asserted, then ADATA_L is asserted if and only if A is asserted; that is, ADATA_L is a copy of A.

If ASEL is negated, BSEL is asserted and BDATA_L is a copy of B. In other words, DATA is a copy of A if ASEL is asserted, and DATA is a copy of B if ASEL is negated. Even though there are five inversion bubbles in the logic diagram, we mentally had to perform only one negation to understand the circuit that BSEL is asserted if ASEL is not asserted.

If we wish, we can write an algebraic expression for the DATA output. We use the technique of Section 4.2, simply propagating expressions through gates toward the output.

In doing so, we can ignore pairs of inversion bubbles that cancel, and directly write the expression shown in color in the figure.. Figure 5-12 Another properly drawn logic diagram. GO = READY_L REQUEST_L = READY REQUEST ENABLE_L = none for none (TEST + (READY REQUEST) ) ENABLE = TEST + (READY REQUEST). TEST LOCK_L HALT = LOC K + (READY REQUEST) . Copyright 1999 by John F. Wakerly Copying Prohibited Section 5.1 Documentation Standards Another ex none none ample is shown in Figure 5-12. Reading directly from the logic diagram, we see that ENABLE_L is asserted if READY_L and REQUEST_L are asserted or if TEST is asserted. The HALT output is asserted if READY_L and REQUEST_L are not both asserted or if LOCK_L is asserted.

Once again, this example has only one place where a gate input s active level does not match the input signal level, and this is reflected in the verbal description of the circuit. We can, if we wish, write algebraic equations for the ENABLE_L and HALT outputs. As we propagate expressions through gates towards the output, we obtain expressions like READY_L REQUEST .

However, we can use our active-level naming convention to simplify terms like READY_L . The circuit contains no signal with the name READY; but if it did, it would satisfy the relationship READY = READY_L according to the naming convention. This allows us to write the ENABLE_L and HALT equations as shown.

Complementing both sides of the ENABLE_L equation, we obtain an equation that describes a hypothetical active-high ENABLE output in terms of hypothetical active-high inputs. We ll see more examples of bubble-to-bubble logic design in this and later chapters, especially as we begin to use larger-scale logic elements. 5.

1.6 Drawing Layout Logic diagrams and schematics should be drawn with gates in their normal orientation with inputs on the left and outputs on the right. The logic symbols for larger-scale logic elements are also normally drawn with inputs on the left and outputs on the right.

A complete schematic page should be drawn with system inputs on the left and outputs on the right, and the general flow of signals should be from left to right. If an input or output appears in the middle of a page, it should be extended to the left or right edge, respectively. In this way, a reader can find all inputs and outputs by looking at the edges of the page only.

All signal paths on the page.
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