High-level test synthesis in Java Embed Code 3 of 9 in Java High-level test synthesis

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743 752.. System-on-a-chip test synthesis In this chapte none none r, we discuss test generation and design for testability methods for a system-on-a-chip. There are three main issues that need to be discussed: generation of precomputed test sets for the cores, providing access to cores embedded in a systemon-a-chip, and providing an interface between the cores and the chip through a test wrapper. We rst brie y discuss how cores can be tested.

This is just a summary of the many techniques discussed in the previous chapters which are applicable in this context. We then present various core test access methods: macro test, core transparency, direct parallel access, test bus, boundary scan, partial isolation ring, modi cation of user-de ned logic, low power parallel scan, testshell and testrail, and the advanced microcontroller bus architecture. We nally wrap this chapter up with a brief discussion of core test wrappers.

. Introduction Spurred by an none none ever-increasing density of chips, and demand for reduced time-tomarket and system costs, system-level integration is emerging as a new paradigm in system design. This allows an entire system to be implemented on a single chip, leading to a system-on-a-chip (SOC). The key constituents of SOCs are functional blocks called cores (also called intellectual property).

Cores can be either soft, rm or hard. A soft core is a synthesizable high-level or behavioral description that lacks full implementation details. A rm core is also synthesizable, but is structurally and topologically optimized for performance and size through oorplanning (it does not include routing).

A hard core is a fully implemented circuit complete with layout. A whole range of cores, such as processors, microcontrollers, interfaces, multimedia, and communication/networking cores, are being used in SOCs. They also cover different types of technology, such as logic, memory and analog.

Some cores are hierarchical, consisting of one or more simpler cores. A core-based SOC is typically composed of a number of large cores as well as some user-de ned logic (UDL) modules connected together by glue logic. Typically, hard cores come with precomputed test sets from the core provider.

For rm and soft cores, such test sets can be obtained by the system integrator. However,. System-on-a-chip test synthesis Source test access mechanism Embedded core Core test wrapper test access mechanism Sink Figure 16.1 Te sting of embedded cores (Zorian et al., 1998) ( c 1998 IEEE).

once these cor none for none es are connected together in a system by the system integrator, it becomes very dif cult to justify these precomputed test sets at the inputs of the cores from system primary inputs and propagate their test responses to system primary outputs. A way of getting around this problem is to use extra design for testability (DFT) hardware to facilitate testing. In this chapter, we describe how one can attack the SOC testing problem (Zorian, 1997; Zorian et al.

, 1998). The main problems in SOC testing involve the design and development of core-level test, core test access and core test wrapper. Core-level test refers to the techniques used in testing cores individually.

Core test access involves methods for accessing the embedded cores in the SOC from the test vector source and propagating its response to a test vector sink. The core test wrapper forms the interface between the embedded core and its SOC environment. Conceptually, these three elements of test can be viewed as shown in Figure 16.

1. These elements can be implemented in various ways, as discussed next..

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